In the field of semiconductor memory devices, it is necessary to minimize the surface of the memory cell array to achieve high integration. A representative example requiring the above-mentioned conditions is a dynamic random access memory (DRAM) comprising one transistor and one capacitor. Since the capacitor occupies the majority of the limited chip surface, it is necessary to minimize the occupying surface of the capacitor. At the same time, the capacitance must be increased to achieve an easier information detection.
FIGS. 1A through 1D illustrate a conventional U-shaped DRAM cell capacitor fabrication process. The cylinder-shaped construction is directed to maximizing the effective surface of the capacitor without expanding the memory cell region. As shown in FIG. 1A, a field oxide 1 is grown at a device isolation region of the p-type silicon substrate S. A gate insulation film 2 and a gate 3 are formed, and a source/drain region, which is a diffusion region of a cell capacitor, within a substrate S at the left/right side of the gate 3 to form a switching transistor.
A first CVD oxide film 5 is formed at the surface of the substrate S including the gate 3. A predetermined portion of the first CVD oxide film 5 is etched using a bit contact mask so as to expose a predetermined portion of the substrate S between the gates 3. A bit line 6, which is a conductive film, is formed so as to connect each drain region of the switching transistor.
A second CVD oxide film 5' is formed on the first CVD oxide film 5 including the bit line 6, and a CVD nitride film 8, serving as an etch stopper film, is formed on the second CVD oxide film 5'. The etch stopper film 8 and the second and first CVD oxide film 5' and 5 are etched so as to expose a predetermined portion of the surface of the substrate S, using a cell contact mask, to form a contact hole. Hereinafter, the first and second CVD oxide films 5 and 5' are collectively referred to with a new reference numeral 7.
Thereafter, as shown in FIG. 1B, a first conductive film (for example, a poly-silicon) 10 is deposited on the etch stopper film 8 including the contact hole. A CVD oxide film, which serves as a second insulation film 11, is formed on the first conductive film 10. Spaced-apart photoresist patterns 12, which are to be used as a node mask, are formed thereon, and the second insulation film 11 and the first conductive film 10 are etched using the photoresist pattern 12 as a mask. Thus, a horizontal node electrode is formed.
Further, as shown in FIG. 1C, the photoresist pattern 12 is removed, a second conductive film (for example, a poly-silicon) 13 is deposited on the etch stopper film 8, including the side surface of the horizontal node electrode and the second insulation film 11, and is dry-etched. Thus, a vertical node electrode is formed. At this time, the surface of the etch stopper there is a limitation in increasing the surface of the capacitor.